--
-- VHDL Architecture Fietssimulator_lib.OR_2.v
--
-- Created:
--          by - jcmooije.UNKNOWN (dtp7985)
--          at - 13:23:12 31-05-2010
--
-- using Mentor Graphics HDL Designer(TM) 2007.1 (Build 19)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY s_OR_2 IS
  PORT(
    a : IN   STD_LOGIC;
    b : IN   STD_LOGIC;
    y : OUT   STD_LOGIC
    );
  END ENTITY s_OR_2;
  
  --
  ARCHITECTURE v OF s_OR_2 IS
  BEGIN
    
    y <= a OR b;
    
    
  END ARCHITECTURE v;
  
  
  